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Obsolete - Not Recommended for New Designs
U630H16P
HardStore 2K x 8 nvSRAM
Features Description The U630H16P has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U630H16P is a fast static RAM (35 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through the state of the NE pin or through software sequences. The U630H16P combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
* * * * * * * * * * * * * * *
*
High-performance CMOS nonvolatile static RAM 2048 x 8 bits 35 ns Access Times 20 ns Output Enable Access Times Hardware and Software STORE Initiation (STORE Cycle Time < 10 ms) Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Hardware and Software RECALL Initiation (RECALL Cycle Time < 20 s) Unlimited RECALL cycles from EEPROM Unlimited Read and Write to SRAM Single 5 V 10 % Operation Operating temperature ranges: 0 to 70 C -40 to 85 C QS 9000 Quality Standard ESD characterization according MIL STD 883C M3015.7-HBM (classification see IC Code Numbers) Package: PLCC32
Pin Configuration
(VCC) VCC n.c. NE A7 W n.c.
Pin Description
Signal Name A0 - A10
29 28 27 26 25 24 23 22 21 A8 A9 n.c. n.c. G A10 E DQ7 DQ6
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Nonvolatile Enable Power Supply Voltage Ground not connected Power Supply Voltage (optional)
4 A6 A5 A4 A3 A2 A1 A0 n.c. DQ0 5 6 7 8 9 10 11 12 13
3
2
1 32 31 30
DQ0 - DQ7 E G W NE VCC VSS n.c. (VCC)
14 15 16 17 18 19 20 DQ2 VSS (VCC) DQ1 DQ3 DQ4 DQ5
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Block Diagram
EEPROM Array 32 x (64 x 8) STORE Row Decoder A5 A6 A7 A8 A9 SRAM Array 32 Rows x 64 x 8 Columns
Store/ Recall Control
VCC VSS
RECALL
VCC
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Input Buffers
Column I/O Column Decoder
Software Detect
A0 - A10
A0 A1 A2 A3 A4 A10
G NE E W
Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage.
E H L L L
NE
*
W
*
G
*
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
H H H
H H L
H L
*
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type
Symbol VCC VI VO PD Ta Tstg
Min. -0.5 -0.3 -0.3
Max. 7 VCC+0.5 VCC+0.5 1
Unit V V V W C C C
0 -40 -65
70 85 150
a: Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Recommended Operating Conditions Power Supply Voltage Input Low Voltage Input High Voltage
Symbol VCC VIL VIH
Conditions
Min. 4.5
Max. 5.5 0.8 VCC+0.3
Unit V V V
-2 V at Pulse Width 10 ns permitted
-0.3 2.2
C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc Average Supply Current during STOREc ICC2 VCC E W VIL VIH VCC E tc Average Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 VCC W VIL VIH VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 V = 2.2 V = 35 ns = 5.5 V VCC-0.2 V VCC-0.2 V 0.2 V VCC-0.2 V = 5.5 V VIH = 35 ns = 5.5 V VCC-0.2 V 0.2 V VCC-0.2 V = 5.5 V VCC-0.2 V 0.2 V VCC-0.2 V 23 15 80 6 Max.
K-Type Unit Min. Max.
85 7
mA mA
Standby Supply Currentd (Cycling TTL Input Levels)
ICC(SB)1
27 15
mA mA
ICC(SB)
1
1
mA
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC VOH VOL Conditions = 4.5 V =-4 mA = 8 mA = 4.5 V = 2.4 V = 0.4 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 0V 1 -1 A A 1 -1 A A Min. Max. Unit
DC Characteristics
Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current
VOH VOL IOH IOL
2.4 0.4 -4 8
V V mA mA
SRAM Memory Operations
No. 1 2 3 4 5 6 7 8 9
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data Validg Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Zh G HIGH to Output in High-Zh E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time after Addr. Changeg
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) tPU tPD 5 0 3 0 Min. 35
35 Unit Max. ns 35 35 20 17 17 ns ns ns ns ns ns ns ns ns 35 ns
10 Chip Enable to Power Activee 11 Chip Disable to Power Standbyd, e
e: f: g: h:
Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or coincident with E transition LOW. Measured 200 mV from steady state output voltage.
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Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
tcR
(1)
Ai DQi
Output Previous Data Valid tv(A) (9)
Address Valid ta(A) (2) Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
tcR (1)
Ai E G DQi
Output
Address Valid ta(A) (2) ta(E) (3) ten(E) (7) ta(G) (4) ten(G) (8) High Impedance tPU (10) ACTIVE STANDBY Output Data Valid tPD (11) tdis(E)
(5)
tdis(G) (6)
ICC
No. Switching Characteristics Write Cycle 12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W LOW to Output in High-Zh, i 23 W HIGH to Output in Low-Z
Symbol Alt. #1 Alt. #2 tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVAV IEC tcW tw(W) tsu(W) tsu(A) Min. 35 30 30 0 30 30 30 18 0 0
35 Unit Max. ns ns ns ns ns ns ns ns ns ns 13 5 ns ns
tAVEH tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
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Write Cycle #1: W-controlledj
tcW
(12)
Ai E W
tsu(A)
Address Valid tsu(E) (17)
th(A) (21)
tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W)
(22)
DQi
Input
(15)
th(D) (20)
DQi
Output
Previous Data
Input Data Valid ten(W) (23) High Impedance
Write Cycle #2: E-controlledj
tcW (12)
Ai E W DQi
Input ten(E) (7) tsu(A) (15)
Address Valid tw(E) (18)
th(A) (21)
tsu(W) (14) tsu(D) (19) tdis(W) (22) th(D) (20)
Input Data Valid High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: j:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W and NE must be > VIH during address transitions.
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Nonvolatile Memory Operations
No. 24
STORE Cycle Inhibit and Automatic Power Up RECALL Power Up RECALL Durationk, e Low Voltage Trigger Level
Symbol Min. Alt. tRESTORE VSWITCH 4.0 IEC 650 4.5 s V Max. Unit
k:
tRESTORE starts from the time VCC rises above VSWITCH.
STORE Cycle Inhibit and Automatic Power Up RECALL VCC 5.0 V VSWITCH
t STORE inhibit Power Up RECALL
(24)
tRESTORE
Hardware Mode Selection
E L L L L * H or L
l:
W H L L H
G L H L H
NE L L L
*
Mode Nonvolatile RECALL Nonvolatile STORE No operation
Power Active ICC2 Active
Notes l
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly.
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STORE Cycles Symbol No. STORE Cycle W-controlled Alt. 25 26 27 28 29 STORE Cycle Timem STORE Initiation Cycle Timen Output Disable Setup to NE Fall NE Setup Chip Enable Setup tWLQX tWLNH tGHNL tNLWL tELWL IEC td(W)S tw(W)S tsu(G)S tsu(N)S tsu(E)S 25 5 5 5 10 ms ns ns ns ns Min. Max. Unit
STORE Cycle: W-controlledo NE G W
tsu(E)S (29)
tsu(G)S tsu(N)S
(27) (28)
tw(W)S (26)
E DQi
Output td(W)S (25) High Impedance
Symbol No. STORE Cycle E-controlled Alt. 30 31 32 33 34 STORE Cycle Time STORE Initiation Cycle Time Output Disable Setup to E Fall NE Setup Write Enable Setup tELQXS tELNHS tGHEL tNLEL tWLEL IEC td(E)S tw(E)S tsu(G)S tsu(N)S tsu(W)S 25 5 5 5 10 ms ns ns ns ns Min. Max. Unit
STORE Cycle: E-controlledo
tsu(N)S
NE G W E DQi
Output
(33)
tsu(G)S (32) tsu(W)S (34) tw(E)S (31) td(E)S (30) High Impedance
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RECALL Cycles Symbol No. RECALL Cycle NE-controlled Alt. 35 36 37 38 39 40 RECALL Cycle Timep RECALL Initiation Cycle Timeq Output Enable Setup Write Enable Setup Chip Enable Setup NE Fall to Output Inactive tNLQX tNLNH tGLNL tWHNL tELNL tNLQZ IEC td(N)R tw(N)R tsu(G)R tsu(W)R tsu(E)R tdis(N)R 25 5 5 5 25 20 s ns ns ns ns ns Min. Max. Unit
RECALL Cycle: NE-controlledo NE
tsu(G)R tw(N)R (36)
G W E
(37)
tsu(W)R
(38)
tdis(N)R (40) td(N)R (35) High Impedance
tsu(E)R (39)
DQi
Output
Symbol No. RECALL Cycle E-controlled Alt. 41 42 43 44 45 RECALL Cycle Time RECALL Initiation Cycle Time NE Setup Output Enable Setup Write Enable Setup tELQXR tELNHR tNLEL tGLEL tWHEL IEC td(E)R tw(E)R tsu(N)R tsu(G)R tsu(W)R 25 5 5 5 20 s ns ns ns ns Min. Max. Unit
RECALL Cycle: E-controlledo
tsu(N)R
NE G W E DQi
Output
(43)
tsu(G)R (44)
tsu(W)R
(45)
tw(E)R (42) td(E)R (41)
High Impedance
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Symbol No. RECALL Cycle G-controlled Alt. 46 47 48 49 50 RECALL Cycle Time RECALL Initiation Cycle Time NE Setup Write Enable Setup Chip Enable Setup tGLQXR tGLNH tNLGL tWHGL tELGL IEC td(G)R tw(G)R tsu(N)R tsu(W)R tsu(E)R 25 5 5 5 20 s ns ns ns ns Min. Max. Unit
RECALL Cycle: G-controlledo, r
tsu(N)R
NE G
(48)
tw(G)R (47)
W E
tsu(W)R (49) tsu(E)R (50) td(G)R (46)
DQi
Output
High Impedance
m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by V CC < VSWITCH (STORE inhibit). n: Once tw(W)S has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to terminate the STORE initiation cycle. o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated. For E-controlled STORE during tw(E)S W, G, NE have to be static. p: Measured with W and NE both HIGH, and G and E LOW. q: Once tw(N)R has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. r: If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
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Software Mode Selection A10 - A0 (hex) 000 555 2AA 7FF 0F0 70F 000 555 2AA 7FF 0F0 70E
E L
W H
Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power Active
Notes s, t s, t s, t s, t s, t s s, t s, t s, t s, t s, t s
ICC2 Active
L
H
s:
t:
The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C. I/O state assumes that G VIL. Activation of nonvolatile cycles does not depend on the state of G.
Symbol
25
Min. Max. Min.
35
Max. Min.
45
Unit Max.
No. Software Controlled STORE/RECALL Cycles, u 25 STORE/RECALL Initiation Time 26 Chip Enable to Output Inactivev 27 STORE Cycle Timew 28 RECALL Cycle Timel 29 Address Setup to Chip Enablex 30 Chip Enable Pulse Widthx, y 31 Chip Disable to Address Changex
Alt.
IEC
tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN
tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
25 600 10 20 0 20 0
35 600 10 20 0 25 0
45 600 10 20 0 35 0
ns ns ms s ns ns ns
u: v: w: x: y:
The software sequence is clocked with E controlled READs. Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit). Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated.
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Software Controlled STORE/RECALL Cyclex, y, z, aa (E = HIGH after STORE initiation)
tcR (25) ADDRESS 6 tw(E)SR (31) th(A)SR
(30) (31)
tcR (25)
Ai E
tsu(A)SR (29)
ADDRESS 1 tw(E)SR
(30)
tdis(E) (5) td(E)R (28)
DQi
Output
th(A)SR High Impedance VALID
tsu(A)SR
(29)
td(E)S (27) VALID tdis(E)SR (26)
Software Controlled STORE/RECALL Cyclex, y, z, aa (E = LOW after STORE initiation)
tcR (25)
Ai E DQi
Output
(29)
ADDRESS 1 tw(E)SR
(30) (31) (29)
ADDRESS 6
(31) th(A)SR
tsu(A)SR High Impedance
th(A)SR
VALID
tsu(A)SR
td(E)S (27) td(E)R (28) VALID tdis(E)SR (26)
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U630H16P performs a STOREor RECALL. aa: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
z:
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Test Configuration for Functional Check
5V VCCac
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Input level according to the
relevant test measurement
VIH
VIL
ment of all 8 output pins
Simultaneous measure-
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
480
VO 30 pF ab 255
NE E W G
VSS
ab: In measurement of tdis-times and ten-times the capacitance is 5 pF. ac: Between V CC and VSS must be connected a high frequency bypass capacitor 0.1 F to avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions VCC VI f Ta = 5.0 V = VSS = 1 MHz = 25 C
Symbol CI CO
Min.
Max. 8 7
Unit pF pF
All pins not under test must be connected with ground by capacitors. Ordering Code Example Type ESD Class blank > 2000 V Package P = PLCC32 Operating Temperature Range C = 0 to 70 C K = -40 to 85 C U630H16 P C 35 Leadfree Option blank = Standard Package G1 = Leadfree Green Package ad Access Time 35 = 35 ns
Device Marking (example)
Product specification
ZMD U630H16PC 35 Z 0425 G1
Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package
Internal Code
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Device Operation The U630H16P has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The U630H16P performs a READ cycle whenever E and G are LOW while W and NE are HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or NE is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW and NE is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The U630H16P is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise problems. Hardware Nonvolatile STORE A STORE cycle is performed when NE, E and W are LOW while G is HIGH. While any sequence to achieve this state will initiate a STORE, only W initiation and E initiation are practical without risking an unintentional STK Control #ML0037 A RECALL cycle is performed when E, G and NE are LOW while W is HIGH. Like the STORE cycle, RECALL is initiated when the last of the three clock-signals goes to the RECALL state. Once initiated, the RECALL cycle will take RECALL Cycle Time" to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on some control pins to cause a RECALL, preventing inadvertend multi-triggering. Software Nonvolatile STORE The U630H16P software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U630H16P implements nonvolatile operation while remaining compatible with standard 2K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0 - 7 pins are tristated until the cycle is completed. If E and G are LOW and W and NE are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, indicating the end of the STORE. Hardware Nonvolatile RECALL
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Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Hardware Protection The U630H16P offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the U630H16P offers hardware protection through VCC Sense. When VCC < VSWITCH the externally initiated STORE operation will be inhibited. Low Average Active Power The U630H16P has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items:
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Automatic Power Up RECALL On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below VSWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds VSWITCH. If the U630H16P is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 K resistor should be connected between W and system VCC.
1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
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U630H16P
LIFE SUPPORT POLICY Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose.
LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek's warranty on any product beyond that set forth in its standard terms and conditions of sale. Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
March 31, 2006
Change record
Date/Rev 10.05.2004 31.3.2006 1.0 Name Matthias Schniebel Troy Meester Simtek Change initial release based on U630H16PA35 and U630H16 integrating software controlled Store / Recall (as U631H16) changed to obsolete status Assigned Simtek Document Control Number

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